1. Field of the Invention
The present invention relates generally to a two-dimensional solid-state image sensor device and more particularly to a two-dimensional solid-state image sensor device of the type in which each picture cell consists of a static induction transistor which functions as photodetector and switching element and in which a plurality of such picture cells are two-dimensionally arranged in a mosaic array.
2. Description of the Prior Art
In a conventional solid-state image sensor device, each picture cell comprises a diode for sensing a light image and a switching transistor. That is, a light image is detected by the diode and the sensed signal per se is outputted as video signal. As a result, the conventional solid-state image sensor device has disadvantages in that the signal output is small and its sensitivity is low. Thus, the degree of integration of the conventional image sensor is limited in terms of sensitivity.
The applicant has disclosed, in Japanese Patent Application No. 204656/1981, a solid-state image sensor device of the type in which a static induction transistor with a high light sensitivity is used so that a light signal is stored in its gate region and a video signal is derived by controlling the current flowing between the source and the drain in response to the potential at the gate region, whereby a high signal output is obtained.
FIG. 1 shows a sectional view of an embodiment of a picture cell used in the above-described solid-state image sensor device. In FIG. 1, reference numeral 1 designates a silicon n.sup.+ substrate; 2, an n.sup.- (or intrinsic) semiconductor region which has a high resistance and serves as channel; 3, an n.sup.+ drain region which has a high impurity concentration and serves as drain region; 4-1 and 4-2, p.sup.+ regions which have a high impurity concentration and are formed so as not to interrupt the channel region and serve as a control gate and a shielding gate, respectively; and 6, an insulation layer or film such as an SiO.sub.2 or Si.sub.3 N.sub.4 film for providing a capacitor over the control gate region. 7, 8 and 10 are gate, drain and source electrodes. At least the gate electrode 7 is transparent to an incident light 18. 9 is surface protection layer or film such as SiO.sub.2.
Reference numeral 11 designates a switching transistor; .phi..sub.s, a control signal applied thereto; 13, a selection line for applying a read pulse voltage .phi..sub.G to the gate electrode 7 from a picture cell selection circuit (not shown); 14, a load resistor; 15, a video voltage supply; 16, a signal readout line; 17, an output terminal; and 18, a light input.
Of the two gate regions 4-1 and 4-2, the p.sup.+ region 4-1 is the control gate which controls the current flow between the source and the drain in accordance with the storage of charge induced in response to the light input. The control gate 4-1 together with the insulating layer or film 6 and the electrode 7 contstitute a capacitor. Another p.sup.+ region 4-2 is the shielding gate and surrounds the control gate 4-1 and the n.sup.+ drain region 3. The control gate 4-1 and the shielding gate 4-2 produce a potential barrier in the channel.
While FIG. 1 shows the structure of only one picture cell, it should be noted that when many picture cells are formed, the shielding gate 4-2 serves to isolate one picture cell from others by a depletion layer. A potential may be applied to the shielding gate 4-2. Alternatively, the shielding gate 4-2 may be grounded through a resistor.
FIG. 2 shows an equivalent circuit of the picture cell shown in FIG. 1 and the operation of the picture cell will be explained with reference to FIG. 2.
When the input light 18 is incident to the picture cell, the light excited holes are stored in the gate regions 4-1 so that the light signal is written therein.
Next, when the pulse voltage .phi..sub.s is applied to the base (or gate) of the transistor 11, the voltage at the power supply 15 is applied across the source and the drain of the static induction transistor 100 as shown in FIG. 1 and if the pulse voltage .phi..sub.G is further applied to the gate region 4 so that the static induction transistor 100 becomes conductive, the drain current corresponding to the light input 18 is derived from the output terminal 17. The output signal derived from the output terminal 17 varies depending upon the intensity of the light input 18. The amplification factor of the static induction transistor 100 is higher than 10.sup.3 which is higher at least by one order than a conventional bipolar transistor. Furthermore, the dynamic range of the output signal is large. The capacitor which is connected to the gate is provided in order to block the direct current and to store the light signal.
While the picture cell per se of the solid-state image sensor device of the type described above has various advantageous properties as described above, the inventors have found that a novel readout process is required when a plurality of picture cells of the type described above are two-dimensionally arranged to form a two-dimensional solid-state image sensor device.
The reasons follow in detail. When a television signal is obtained from the two-dimensional solid-state image sensor device, the storage and readout of the video signal must be repeated carried out per field or frame unit. It follows, therefore, that the video signal is required to be stored in each cell after the readout of the video signal from one picture cell or from each of the picture cells arranged in one horizontal line (corresponding to one horizontal scanning) is completed and before the readout of the video signal from the same one picture cell or from each of the same picture cells arranged in the same one horizontal line during the next field or frame. Therefore, immediately after the readout from one picture cell or from each of the picture cells arranged in one horizontal line is completed, it is necessary that the same picture cell is refreshed (cleared) and the storage of a new video signal starts.
In a conventional two-dimensional solid-state image sensor device the type in which photodiodes and MOS transistor are combined, carriers corresponding to the intensity of light incident to the photodiode are supplied to the source junction of the MOS transistor, while the MOS transistor is interrupted, thereby rendering the MOS transistor conductive. Simultaneously, a transistor which is connected to the drain of the MOS transistor is rendered conductive so that a charge current flows from the drain to the source. An output signal is obtained depending upon an amount of the charge current. Therefore, the readout process of one picture cell corresponds to the refreshment of that picture cell. Thus, a video signal can be obtained by rendering either of the pulse .phi..sub.G or .phi..sub.s ON precedingly; i.e., the pulse .phi..sub.G to be applied to the gate of the MOS transistor or the pulse .phi..sub.s to be applied to the gate of a transistor connected between the drain of the MOS transistor and a terminal of a video power supply (serving also as an output terminal).
On the other hand, in the above-described solid-state image sensor device of the type in which the light signal is stored in the gate region of the static induction transistor and the video signal is derived therefrom by controlling the current flowing between the source and the drain in response to the potential of the gate region, it is impossible to store a new video signal unless the video signal stored in the gate region is refreshed immediately after the video signal is readout. As a result, the video signal cannot be obtained.
With this in view, the image sensor device of this type employs the circuit arrangement as shown in FIG. 3 in which a vertical scanning circuit 20 is used to sequentially select read lines 16-1, 16-2, . . . , and 16-L while a horizontal scanning circuit 21 is used to sequentially select lines 13-1, 13-2, . . . , and 13-K. As illustrated in FIG. 4, in response to the pulse .phi..sub.s1, the read line 16-1 is selected and during the period of this pulse .phi..sub.s1, the pulses .phi..sub.G1, .phi..sub.G2, . . . , and .phi..sub.GK are sequentially selected. The video signal in the picture cells (1-1), (2-1), . . . , and (K-1) which are connected to the read line 16-1 are read out. Thereafter in response to the next pulse .phi..sub.s2, the read line 16-2 is selected and during the period of this pulse .phi..sub.s2, the pulses .phi..sub.G1, .phi..sub.G2, . . . , and .phi..sub.GK are sequentially selected. When the pulses .phi..sub.s3, .phi. .sub.s4, . . . , and .phi..sub.sL are sequentially selected in this manner, the light signals stored in the respective gate regions 4-1 of the picture cells (1-1), (2-1), . . . , and (K-1) which are connected to the read line 16-1, of which the read out selection is completed, will not be refreshed at all. Therefore, in order to refresh the gate regions 4-1 of these picture cells (1-1), (2-1), . . . , and (K-1) which are connected to the read line 16-1, it may be proposed to increase the voltage level of the gate pulses .phi..sub.G1, .phi..sub.G2, . . . , and .phi..sub.GK so that the light signals stored in the gate regions 4-1 are discharged. In this case, however, all the light signals stored in the picture cells connected in common to the selection line 13-1, 13-2, . . . , and 13-K are also discharged, so that it is impossible to attain the two-dimensional image readout.